Quantum Simulator for Entangled Nano-Electronics (QSEE)

Partners: University of Glasgow (V. Georgiev)

EPSRC £600K June 2018 to December 2021

Counterfeit products, particularly cloning of different electronics devices, are emerging as a significant problem in many industries and technologies. One way to approach this problem is to create Physical Uncloneable Functions (PUFs). They are a relatively recent invention providing an alternative method to generate secrets for unique identification or cryptographic key generation. Instead of storing the secret in digital memory, or asking a user to provide it, it is derived from a physical characteristic of the system. The assumption is that the secret cannot be copied, as it is bound to a physical entity which cannot be cloned. Furthermore, it is assumed that the probability of finding two devices with identical physical characteristics is very low. Hence, using this atomistic variability could create unique fingerprints which can be used to securely and precisely identify a specific device or an object.

As a result, PUFs have the potential to revolutionise the way that resource-constrained (e.g. IoT) devices are authenticated. When compared to existing solutions they offer small footprints, use fewer resources and provide much greater security. Existing demonstrations of PUFs have been limited, however, and results are constrained by statistics. A lack of validation through large-scale testing or simulations is a significant barrier to adoption. Hence, one of the aims of this proposal is to address this issue.

In this fellowship, two possible structures will be explored as a PUF: a Resonant Tunnelling Diode (RTD) and a Single Electron Transistor (SET). Both devices encapsulate a quantum nanostructure. RTDs and SETs display an exotic I-V characteristic not seen in classical devices, with the nanostructure only allowing electrons to exist at well-defined energy levels. Current can only flow through the device at these energies, thus, this type of devices allows current to flow only at well-defined voltages. These voltage peaks are highly dependent on the quantum confinement exhibited within the nanostructure, which is subject to the overall atomic arrangement of the device. Hence, the device output is directly linked to atom-scale variations and could be used as unique ‘fingerprints’ to distinguish each device. Moreover, the devices at the heart of this proposal (RTD and SET) are compatible with the current CMOS technology. It can be manufactured from a wide range of materials, at different scales and in different configurations. However, finding the optimal design for incorporation into existing fabrication processes by trial and error would be time consuming and expensive. This is a significant barrier to exploitation of those devices. Hence, the other aim of this fellowship is to overcome this significant barrier by combining theory and simulations with experiments, addressing fundamental issues and providing insight that leads to improvement of the fabrication processes.

This project brings together three UK company and one research groups in the University of Glasgow to deliver progress in the field of improving the design parameters and performance of RTDs and SETs for a specific PUF application.

Link to the website: https://gow.epsrc.ukri.org/NGBOViewGrant.aspx?GrantRef=EP/S001131/1